1 ? fn3147.3 HI-518 8-channel/differential 4-channel, cmos high speed analog multiplexer the hl-518 is a monolithic, dielectrically isolated, high speed, high performance cmos analog multiplexer. it offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. the dual function of address input a 2 enables the hl-518 to be user programmed either as a single ended 8-channel multiplexer by connecting ?out a? to ?out b? and using a 2 as a digital address input, or as a 4-channel differential multiplexer by connecting a 2 to the v- supply. the substrate leakag es and parasitic capacitances are reduced substantially by using the intersil dielectric isolation process to achieve optimum performance in both high and low level signal applications. the low output leakage current (l d(off) < 100pa at 25 o c) and fast settling (t settle = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. features ? access time (typical) . . . . . . . . . . . . . . . . . . . . . . 130ns ? settling time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%) ? low leakage (typical) -i s(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pa -i d(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15pa ? low capacitance (max) -c s(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pf -c d(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pf ? off isolation at 500khz . . . . . . . . . . . . . . . . . . 45db (min) ? low charge injection error . . . . . . . . . . . . . . . . . . . 25mv ? single ended to differential selectable (sds) ? logic level selectable (lls) applications ? data acquisition systems ? precision in strumentation ? industrial control pinout HI-518 (cerdip, pdip) top view ordering information part number temp. range ( o c) package pkg. dwg. # hi3-0518-5 0 to 75 18 ld pdip e18.3 hi1-0518-8 -55 to 125 18 ld cerdip f18.3 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 out a in4/4a in3/3a in2/2a in1/1a enable a 0 v- a 1 v+ out b in8/4b in7/3b in6/2b in5/1b v dd /lls gnd a 2 /sds data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved
2 functional block diagram truth tables table 1. HI-518 used as an 8-channel multiplexer or dual 4-channel multiplexer (note 1) use a 2 as digital address input on channel to enable a 2 a 1 a 0 out a out b l x x x none none h lll 1a none h l l h 2a none h l h l 3a none h l h h 4a none h h l l none 1b h h l h none 2b h h h l none 3b h hhhnone 4b note: 1. for 8-channel single ended function, tie ?out a? to ?out b?; for dual 4-channel function, use the a 2 address pin to select between mux a and mux b, where mux a is selected with a 2 low. table 2. HI-518 used as a differential 4-channel multiplexer a 2 connected to v- supply on channel to enable a 1 a 0 out a out b l x x none none hll1a1b hlh2a2b hhl3a3b hhh4a4b a 2 decode a 2 qq hhml llh v- l l a 2 decoder n p n p in 1a out a in 4a n p n p in 1b out b in 4b v dd /lls multiplexer switches input buffer and decoders q q en a 0 a 1 a 2 decoder decoder HI-518
3 absolute maximum rati ngs thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33v analog (v in , v out ) . . . . . . . . . . . . . . . . . . . . . . (v-) -2v to (v+) +2v digital input voltage: ttl levels selected (v dd /lls pin = gnd or open) v a0-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +6v v a2/sds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v-) -2v to (v+) +2v cmos levels selected (v dd /lls pin = v dd ) v a0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to (v+) +2v operating conditions temperature ranges HI-518-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c HI-518-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 2) . . . ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 90 n/a cerdip package. . . . . . . . . . . . . . . . . 70 18 maximum junction temperature ceramic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v; v dd /lls = gnd (note 3), unless otherwise specified parameter test conditions temp ( o c) -8 -5 units min typ max min typ max dynamic characteristics access time, t a 25 - 130 175 - 130 175 ns full--225--225ns break-before-make delay, t open 25 10 20 - 10 20 - ns enable delay (on), t on(en) 25 - 120 175 120 175 ns enable delay (off), t off(en) 25 - 140 175 140 175 ns settling time to 0.1% 25 - 250 - - 250 - ns to 0.01% 25 - 800 - - 800 - ns charge injection error note 6 25 - - 25 - - 25 mv off isolation note 7 25 45 - - 45 - - db channel input capacitance, c s(off) 25 - - 5 - - 5 pf channel output capacitance, c d(off) 25 - - 10 - - 10 pf digital input capacitance, c a 25 - - 5 - - 5 pf input to output capacitance, c ds(off) 25 -0.02- -0.02- pf digital input characteristics input low threshold, v al (ttl) note 3 full - - 0.8 - - 0.8 v input high threshold, v ah (ttl) note 3 full 2.4 - - 2.4 - - v input low threshold, v al (cmos) note 3 full - - 0.3v dd - - 0.3v dd v input high threshold, v ah (cmos) note 3 full 0.7v dd - - 0.7v dd --v input leakage current, i ah (high) full - - 1 - - 1 a input leakage current, i al (low) full - - 20 - - 20 a analog channel characteristics analog signal range, v in note 4 full -14 - +14 -15 - +15 v on resistance, r on note 5 25 - 480 750 - 480 750 ? full - - 1,000 - - 1,000 ? off input leakage current, l s(off) 25 -0.01- -0.01- na full - - 50 - - 50 na off output leakage current, i d(off) 25 - 0.015 - - 0.015 - na full - - 50 - - 50 na on channel leakage current, i d(on) 25 - 0.015 - - 0.015 - na full - - 50 - - 50 na power supply characteristics power dissipation, p d full--450--540mw HI-518
4 i+, current v en = 2.4v full - - 15 - - 18 ma i-, current full - - 15 - - 18 ma notes: 3. v dd /lls pin = open or grounded for ttl compatibility. v dd /lls pin = v dd for cmos compatibility. 4. at temperatures above 90 o c, care must be taken to assure v in remains at least 1.0v below the v supply for proper operation. 5. v in = 10v, i out = -100 a. 6. v in = 0v, c l = 100pf, enable input pulse = 3v, f = 500khz. 7. c l = 40pf, r l = 1k, v en = 0.8v, v in = 3v rms , f = 500khz. due to the pin to pin capacitance between in 8/4b and out b, channel 8/4b exhibits 60db of off isolation under the above test conditions. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v; v dd /lls = gnd (note 3), unless otherwise specified (continued) parameter test conditions temp ( o c) -8 -5 units min typ max min typ max test circuits and waveforms v dd /lls = gnd, unless otherwise specified figure 1. on resistance test circuit figure 2. i d(off) test circuit (note 8) figure 3. i s(off) test circuit (note 8) figure 4. i d(on) test circuit (note 8) figure 5a. measurement poin ts figure 5b. test circuit figure 5. access time note: 8. two measurements per channel: 10v and 10v. (two measurements per device for i d(off) 10v and 10v.) out in v in v 2 i out 100 a r on = v 2 100 a 10v out 10v en 0.8v 10v a i d(off) out en 10v a i s(off) 0.8v 10v out 10v en 2.4v 10v a i d(on) a 2 a 0 50% 3.5v 10% +10v 0v output -10v t a address drive (v a ) 10v +15v v+ v- in 1 in 2-7 in 8 outb a 0 en a 1 10 50 k ? pf -15v a 2 /sds 50 ? v a 2.4v gnd v dd /lls 10v outa HI-518
5 figure 6a. measurement poin ts figure 6b. test circuit figure 6. break-before-make delay figure 7a. measurement poin ts figure 7b. test circuit figure 7. enable delay figure 8a. measurement poin ts figure 8b. test circuit ? v o is the measured voltage error due to charge injection. the error in coulombs is q = c l x ? v o . figure 8. charge injection test circuits and waveforms v dd /lls = gnd, unless otherwise specified (continued) 50% 50% 3.5v 0v output address drive (v a ) t open s 1 on s 8 on +5v +15v v+ v- in 1 in 2-7 in 8 outb a 0 en a 1 12.5pf 800 v out -15v a 2 /sds 50 ? v a 2.4v gnd v dd /lls ? outa 3.5v 0v output t off(en) 50% 90% t on(en) 10% 50% enable drive (v a ) 0v +10v +15v v+ v- in 1 in 2-8 outa a 0 en a 1 12.5pf 800 -15v a 2 /sds 50 v a gnd v dd /lls ? ? 0v ? v o 3v v a v out 2.4v +15v v- a 0 , a 1 , en -15v gnd v dd /lls a 2 /sds in out a or b v out c l = 100pf v a v+ HI-518
6 die characteristics die dimensions: 89 mils x 93 mils metallization: type: alcu thickness: 16k ? 2k ? substrate potential (note) : -v supply passivation: type: nitride over silox nitride thickness: 3.5k ? 1.0k ? silox thickness: 12k ? 2.0k ? worst case current density: 1.43 x 10 5 a/cm 2 transistor count: 356 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left floating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layout HI-518 v+ out b en a 0 a 2 /sds a 1 v dd /lls gnd in 1/1a in 2/2a in 3/3a in 4/4a out a v- in 5/1b in 6/2b in 7/3b in 8/4b HI-518
7 HI-518 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f18.3 mil-std-1835 gdip1-t18 (d-6, configuration a) 18 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.960 - 24.38 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n18 188 rev. 0 4/94
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HI-518 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e18.3 (jedec ms-001-bc issue d) 18 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.845 0.880 21.47 22.35 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n18 189 rev. 0 12/93
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